The invention relates to an automatic exposure control circuit for camera, and more particularly, to an improvement of such control circuit which has the capability to control the amount of light emitted from a flash discharge tube which is operated when taking a picture under flashlight illumination from an electronic flash.
A conventional automatic exposure control circuit for a camera, for example, a control circuit associated with an electrical shutter, includes a comparator which is formed by an integrated circuit of bipolar type. In a comparator of this type, it is recognized that a stray capacitance or junction capacitance across the base, emitter and collector of a transistor which is used in the input stage as well as an inherent lag in the response of a bipolar transistor itself as may be caused by the recombination of electrons and holes result in a lag in the response of the comparator. Where an output signal from such comparator is utilized to interrupt the emission of light from a flash discharge tube contained in an electronic flash, an overexposure may be caused by a time lag involved with the output signal relative to an input signal inasmuch as the output signal is not immediately inverted in response to the inversion of the input signal supplied to the comparator from a photometric circuit if the latter functions properly to determine a proper amount of exposure.
FIG. 1 is a circuit diagram of a control circuit associated with an electrical shutter of a photographic camera, illustrating one form of a conventional automatic exposure control circuit. The control circuit shown includes a photometry controlling switch SW1 which is opened and closed in response to the opening and closing operation of an electrical shutter, a photometric, photoelectric transducer element PD1 which is adapted to provide an automatic exposure control, a bias capacitor C1 in shunt with the transducer element PD1 for applying a voltage thereacross during a photometric operation, a variable resistor VR1 which is utilized to establish a film speed, a voltage divider resistor R1, a comparator CP1 formed by an integrated circuit of bipolar type, a resistor R2 connected to the comparator CP1 for adjusting an input current thereto, an electromagnet Mg1 which is adapted to close an electrical shutter, a switching transistor Q1 connected in series with the electromagnet Mg1 for controlling the latter, an output resistor R5 connected to a terminal T1 at which an illumination control signal is developed for controlling a flash discharge tube, not shown, of an electronic flash, another switching transistor Q2 for supplying or interrupting the application of an operating voltage +Vcc to the output resistor R5, and base resistors R3, R4 associated with the switching transistors Q1, Q2, respectively.
The photometry controlling switch SW1 is connected in series with the transducer element PD1 across a bus E1 which is connected to a power supply, not shown, and to which the operating voltage +Vcc is supplied and a ground bus E0 which is connected to the ground. Also connected across the buses E1, E0 in shunt with the series combination of the switch SW1 and transducer element PD1 are a series circuit including the variable resistor VR1 and voltage divider resistor R1; another series circuit including the switching transistor Q1 and the electromagnet Mg1; and a further series circuit including the switching transistor Q2 and the output resistor R5.
The junction between the controlling switch SW1 and the transducer element PD1 is connected to an inverting input terminal of the comparator CP1 and is also connected to the bus E0 through the bias capacitor C1. The non-inverting input terminal of the comparator CP1 is connected to the junction between the variable resistor VR1 and the resistor R1 while a control terminal of the comparator CP1 is connected to the bus E0 through the input current adjusting resistor R2. It will be seen that the output terminal of the comparator CP1 is connected to the base of each of the transistors Q1 and Q2 through the resistors R3 and R4, respectively. The transistors Q1 and Q2 are of PNP type, and have their emitters connected in common with the bus E1, and their collectors are connected to the bus E0 through the electromagnet Mg1 and the output resistor R5, respectively. The junction between the transistor Q2 and the output resistor R5 is connected to the terminal T1 where an illumination control signal is developed. It is to be noted that the circuit connection of the comparator CP1 with the bus E1 is not shown even though it is fed from this bus to receive the operating voltage +Vcc.
In operation, the switch SW1 is opened as the electrical shutter is opened, whereby the voltage across the charged capacitor C1 is applied to the transducer element PD1 for allowing the latter to initiate its photometric operation. The charge across the capacitor C1 is discharged in accordance with the amount of light input to the transducer element PD1, and when the potential at the inverting input terminal of the comparator CP1 decreases below a reference potential applied to the non-inverting input terminal thereof which is determined by the voltage divider comprising the variable resistor VR1 and the resistor R1, the output from the comparator CP1 inverts from its low level to its high level. Thereupon, the transistor Q1 is turned off to deenergize the electromagnet Mg1, thus causing the electrical shutter to be closed. At the same time, the transistor Q2 is also turned off, whereby the potential at the terminal T1 changes from its high to its low level. This signal is supplied to an illumination control circuit associated with the flash discharge tube of the electronic flash, thus interrupting the emission of light from the discharge tube.
As mentioned previously, the comparator CP1 is formed by an integrated circuit, the internal equivalent circuit of which can be represented in terms of transistors Q3-Q18 and resistors R6-R13 as indicated in FIG. 2. Specifically, an NPN transistor Q3, representing an input stage, has its base connected to an inverting input terminal T2 while an NPN transistor Q4, also in the input stage, has its base connected to a non-inverting input terminal T3. An output stage is formed by an NPN transistor Q18, and the junction between the collector thereof and resistor R13 is connected to an output terminal T4. In this arrangement, the current fed from the inverting and the non-inverting input terminal T2, T3 is determined by the resistance of the current adjusting resistor R2 which is connected to the emitter of an NPN transistor Q7 or to a control terminal T8 of the comparator CP1, and by the base current of transistors Q5, Q6. In the control circuit described above, the resistor R2 has a large ohmic value to reduce the input current since if the ohmic value of the resistor R2 is reduced to allow an increased input current to flow, the charge on the capacitor C1 will be rapidly discharged through the comparator CP1 and the resistor R2, resulting in reducing the dynamic range of the transducer element PD1.
However, it is to be noted that when the magnitude of the input current to the comparator CP1 is decreased, it takes an increased length of time to charge the stray capacitance (or junction capacitance) across the base and emitter and across the base and collector of the transistors Q3, Q4 connected to the input terminals T2, T3, respectively, which are shown by dotted lines in FIG. 2. This results in a slow response of the comparator CP1, presenting a difficulty that the comparator cannot properly respond to a flashlight illumination having a very reduced duration.